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  • Digital Circuit Design Engineer for Automotive SoC Design

    Renesas - Kodaira, Japan
    ... Digital Circuit Design Engineer for Automotive SoC Design Job Description Digital circuit design/management for automotive SoC (R-Car series) Job for building hierarchy which ...

  • ASIC Design for Testability Engineer, Silicon

    Google - Bengaluru, India
    ... . Work on a team of Design for Testing (DFT) engineers, working closely with RTL and Physical Designer ... design DFT techniques used for logic testing. Ability to scale DFT, with a focus on minimal area ...

  • SRAM Circuit Design Engineer

    Apple - Austin, Texas
    ... SRAM Circuit Design Engineer Austin,Texas,United States Hardware Do you have a ... an extraordinary logic/architecture team to formulate design specifications. - Define architecture ...

  • Front-end RTL/Verification Tools & Methodology Engineer

    Intel - San José, Costa Rica
    ... best in class Front End tools, flows and methodology. They work closely with project logic design and ... explore new AI ML tools and solutions to help designer and verifier improve overall design cycle ...

  • SRAM Circuit Design Engineer

    Apple - Austin, Texas
    ... SRAM Circuit Design Engineer Austin,Texas,United States Hardware Do you have a ... an extraordinary logic/architecture team to formulate design specifications. - Define architecture ...

  • Lead CPU RTL Design Engineer, Silicon

    Google - New Taipei City, Taiwan
    ... logic synthesis techniques to optimize RTL code, performance and power as well as low-power design ... equivalent practical experience. 8 years of experience with digital logic design principles ...

  • SoC Logic Design Engineer

    Intel - San José, Costa Rica
    ... transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and ... various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies ...

  • ASIC Engineer, Implementation

    Meta - Bangalore, India
    ... on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer ... Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. Perform RTL ...

  • ASIC Engineer, Implementation

    Meta - Bangalore, India
    ... on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer ... Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. Perform RTL ...

  • SoC RTL Designer Engineer

    Intel - Folsom, California
    ... designs into high volume production SoC Power Management RTL design using Verilog/System Verilog ... validation of discrete graphics SoC products, including: Creating a design to produce key assets ...

  • ASIC Design Engineer - Clocks

    Nvidia - Bengaluru, India
    ... high-speed logic design and gate-level design implementation and optimization! The complexity of ... -end cycle of SOC execution starting from micro-arch, design implementation, design fixes, sign-off ...

  • Silicon Physical Design Engineer

    Actalent - Sunnyvale, California
    ... must have. Experience with RTL Synthesis and design optimization for Power Performance Area ... Description: Run Logic/Physical Synthesis and generate optimized Gate Level Netlist for ...

  • Senior Emulation Engineer

    Intel - Malaysia
    ... with a good understanding of logic design concepts. Verilog, System Verilog. RTL simulation ... Job Description Builds emulation and FPGA models and solutions from RTL design using ...

  • Physical Silicon Design Engineer (India)

    Edgecortix Inc. - Remote, India
    ... Introduction Edgecortix Inc. is seeking a Hardware Design Engineer with proven RTL/logic and ... the architecture and RTL design team providing continuous feedback to architecture and logic ...

  • SoC Design Engineer

    Google - Sunnyvale, California
    ... data centers affecting millions of Google users. As a SoC Design Engineer, you will join a team working on SoC-level RTL design for our data center acclerators. You will design RTL IP with the focus on ...

  • SoC Logic Design Engineer

    Intel - San José, Costa Rica
    ... Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or ...

  • Client Chipsets Full Chip UPF Integration Engineer

    Intel - Malaysia
    ... Job Description Understands the logic of design, register transfer level (RTL) coding, and simulation for an SoC design and integrates UPF (Unified Power Format) of IP blocks and subsystems ...

  • CPU-SoC Silicon Design Engineering Part-Time Intern

    Intel - Malaysia
    ... -voltage I/O, and layout design for Intel's SOC. Integrate third-party IPs into the system, ensuring ... . Validate and integrate third-party IPs, working closely with design teams to implement low-level RTL design ...

  • SOC DFT Design Engineering Graduate Trainee

    Intel - Kulim, Malaysia
    ... opportunity to be trained and to gain exposure to perform SoC design work such as:- RTL logic design in System ... Structural Design, SoC RTL, Architecture/Microarchitecture, IP Design, Post-Silicon Manufacturing and other ...

  • SoC Integration Engineer

    Apple - Austin, Texas
    ... IP integration, sub-system creation and RTL Design for SOC top-level such as IO/PAD-ring, clock and ... SoC Integration Engineer Austin,Texas,United States Hardware At Apple ...

  • SoC Integration Engineer

    Apple - Austin, Texas
    ... IP integration, sub-system creation and RTL Design for SOC top-level such as IO/PAD-ring, clock and ... SoC Integration Engineer Austin,Texas,United States Hardware At Apple ...

  • SoC Design Engineer: ISCP SoC Front-End Design Team

    Intel - Malaysia
    ... Job Description Be a part of IP Security Client Product Group, SoC Front End Design team ... but not limited to: Involving in microarchitecture/RTL logic/testbench/verification ...

  • SoC Design Engineer: ISCP SoC Front-End Design Team

    Intel - Malaysia
    ... Job Description Be a part of IP Security Client Product Group, SoC Front End Design team ... but not limited to: Involving in microarchitecture/RTL logic/testbench/verification ...

  • SOC DFT Engineer

    Intel - Bengaluru, India
    ... Job Description Develops the logic design, register transfer level (RTL) coding ... , tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to ...

  • SOC DFT Engineer

    Intel - Bengaluru, India
    ... Job Description Develops the logic design, register transfer level (RTL) coding ... , tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to ...

  • SoC Power Management RTL Design Engineer

    Intel - Bengaluru, India
    ... Intel and we are looking for a SoC Design Engineer to join our team. In this position you will help us ... implement new features in RTL at IP or SOC level - Collaborate with cross-functional teams (FW, Validation ...

  • Staff SoC Design Engineer: ISCP SoC Front-End Design Team

    Intel - Malaysia
    ... /RTL logic/testbench/verification environment design and integration/debug at various levels.2 ... Intel's client chipsets and SoC products. Collaborate across teams including IP Design, Firmware ...

  • SOC DFT Engineer

    Intel - Bengaluru, India
    ... Job Description Develops the logic design, register transfer level (RTL) coding ... , tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to ...

  • Staff SoC Design Engineer: ISCP SoC Front-End Design Team

    Intel - Malaysia
    ... leadership in microarchitecture/RTL logic/testbench/verification environment design and integration/debug at ... Intel's client chipsets and SoC products. Collaborate across teams including IP Design ...

  • Staff SoC Design Engineer: ISCP SoC Front-End Design Team

    Intel - Malaysia
    ... Intel's client chipsets and SoC products. Collaborate across teams including IP Design, Firmware ... logic/testbench/verification environment design and integration/debug at various levels.2. Involving in ...
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