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Intel Careers 272 Jobs in United States

  • SoC Logic Design Engineer

    Intel - Folsom, California
    ... to: Logic design, Register Transfer Level (RTL) coding, and simulation to generate cell ... development of Architecture and Microarchitecture specifications for the Logic components. Provide IP ...

  • SoC Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... Logic Design Engineer. We are developing the next generation prototype solutions across Supercomputing ... : Working with architects to define, implement the handshake logic between IP and SOC and integrate them ...

  • SoC Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... Job Description Come join the Extreme Scale Computing team as a Logic Design Engineer ... handshake logic between IP and SOC and integrate them. Working with architects and design engineers to ...

  • Logic Design Engineer

    Intel - Folsom, California
    ... Group (CEG) are looking for logic design engineer to work on state-of the art DDR PHY. This team works ... Ips. Performs logic design. Register Transfer Level (RTL) coding, and simulation to generate ...

  • IP Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... wonderful for everyone. DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... help ensure Intel's success in the rapidly growing Cloud Computing and AI domains The IP Logic ...

  • IP Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... wonderful for everyone. DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... help ensure Intel's success in the rapidly growing Cloud Computing and AI domains The IP Logic ...

  • IP Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... wonderful for everyone. DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... help ensure Intel's success in the rapidly growing Cloud Computing and AI domains The IP Logic ...

  • CPU Logic Design Engineer

    Intel - Austin, Texas
    ... knowledge of hardware modeling issues and logic debug environments. Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization ...

  • SoC Logic Design Engineer

    Intel - Hillsboro, Oregon
    ... Logic design. Microarchitecture of global SoC flows such as reset, clocking, power management ...

  • Logic Design Methodology Engineer

    Intel - Phoenix, Arizona
    ... efficiency and quality. As a Logic Design Methodology Engineer you will design, develop, test, and debug ...

  • Mixed-Signal Logic Design Engineer.

    Intel - Hillsboro, Oregon
    ... (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries ...

  • Logic Design Technology Co-optimization (DTCO) Engineer

    Intel - Hillsboro, Oregon
    ... process and product design teams, to deliver capabilities to optimize and integrate digital-logic circuits ... used to target and benchmark digital-logic power and performance associated with the various technology ...

  • SoC Logic Design Engineer - Foundry Services

    Intel - Folsom, California
    ... : Logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries ... Architecture and Microarchitecture specifications for the Logic components. Provide IP integration support ...

  • SoC Logic Design - Undergrad Intern

    Intel - Hillsboro, Oregon
    ... searching for motivated student interns to support Register-Transfer Logic development, using automated ... efficiency of the Register-Transfer Logic development for test chip components.** **The intern will be ...

  • Graduate Intern - HW Logic Design

    Intel - Santa Clara, California
    ... limited to: Design, documentation, and integration of design. Logic design using Verilog and ...

  • Senior SoC Logic Design Engineer - Foundry Services

    Intel - Folsom, California
    ... : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design ...

  • DFX Micro-Architect

    Intel - Folsom, California
    ... (MIP) within the Client Engineering Group (CEG) is looking for a DFX Micro-Architect/Designer to work ... include, but not limited to: Work with Logic and Analog Architects to define HAS (High Level ...

  • Circuit Design Engineer

    Intel - Austin, Texas
    ... Design Enablement (DE) is focused on pathfinding and development of advanced logic, memory, and analog ... Circuits (Wave Guide TX, Power Amplifier) The Person: As a PROM Mixed-Signal Circuit Designer ...

  • SOC Design Engineer

    Intel - Folsom, California
    ... Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or ...

  • Senior Structural (Physical Design) Engineer

    Intel - Santa Clara, California
    ... collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Staff Structural (Physical Design) Engineer - Floorplanning

    Intel - Santa Clara, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Structural Design (Physical Design) Engineer - Lead

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Full Chip STA/Timing Engineer

    Intel - Santa Clara, California
    ... future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • FPGA Silicon Design Engineer

    Intel - San Jose, California
    ... requirements. Prepare and design logic diagrams and codes for implementing system design and test ...

  • Intel Foundry - Full Chip Timing Engineer

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Transistor Reliability RD Engineer

    Intel - Hillsboro, Oregon
    ... future logic process technologies, ensuring the transistors meet reliability requirements. You will ...

  • Senior Structural (Physical Design) Engineer

    Intel - Santa Clara, California
    ... collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Structural Design (Physical Design) Engineer - Lead

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Full Chip Timing Engineer - Lead

    Intel - Folsom, California
    ... future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Physical Design Layout Methodology and Integration Engineer

    Intel - Hillsboro, Oregon
    ... our Design Enablement (DE) and Logic Technology Development (LTD) team for Intel's next generation ...
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