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Intel
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Santa Clara, California
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limited to:
Design, documentation, and integration of design.
Logic design using Verilog and
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Intel
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Santa Clara, California
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following:
Basic understanding of standard cell circuit concepts, including logic gates, flip-flops
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Intel
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Santa Clara, California
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efficient RTL logic design, and DV support
- Running tools to ensure lint-free and CDC/RDC clean design ... in modern design techniques and energy-efficient/low power logic design and power analysis
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Intel
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Santa Clara, California
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study and 6+ years of experience in a related field.
4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators
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