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Intel Careers 70 Jobs in California

  • SoC Logic Design Engineer

    Intel - Folsom, California
    ... to: Logic design, Register Transfer Level (RTL) coding, and simulation to generate cell ... development of Architecture and Microarchitecture specifications for the Logic components. Provide IP ...

  • Logic Design Engineer

    Intel - Folsom, California
    ... Group (CEG) are looking for logic design engineer to work on state-of the art DDR PHY. This team works ... Ips. Performs logic design. Register Transfer Level (RTL) coding, and simulation to generate ...

  • SoC Logic Design Engineer - Foundry Services

    Intel - Folsom, California
    ... : Logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries ... Architecture and Microarchitecture specifications for the Logic components. Provide IP integration support ...

  • Graduate Intern - HW Logic Design

    Intel - Santa Clara, California
    ... limited to: Design, documentation, and integration of design. Logic design using Verilog and ...

  • Senior SoC Logic Design Engineer - Foundry Services

    Intel - Folsom, California
    ... : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design ...

  • DFX Micro-Architect

    Intel - Folsom, California
    ... (MIP) within the Client Engineering Group (CEG) is looking for a DFX Micro-Architect/Designer to work ... include, but not limited to: Work with Logic and Analog Architects to define HAS (High Level ...

  • SOC Design Engineer

    Intel - Folsom, California
    ... Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or ...

  • Senior Structural (Physical Design) Engineer

    Intel - Santa Clara, California
    ... collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Staff Structural (Physical Design) Engineer - Floorplanning

    Intel - Santa Clara, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Structural Design (Physical Design) Engineer - Lead

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Full Chip STA/Timing Engineer

    Intel - Santa Clara, California
    ... future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • FPGA Silicon Design Engineer

    Intel - San Jose, California
    ... requirements. Prepare and design logic diagrams and codes for implementing system design and test ...

  • Intel Foundry - Full Chip Timing Engineer

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Senior Structural (Physical Design) Engineer

    Intel - Santa Clara, California
    ... collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific ... -Chip and (or) partition level physical design (APR digital logic). RTL to gds2 flow and basic ...

  • Structural Design (Physical Design) Engineer - Lead

    Intel - Folsom, California
    ... microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • Full Chip Timing Engineer - Lead

    Intel - Folsom, California
    ... future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design ... ):** Prior experience with Full-Chip and (or) partition level physical design (APR digital logic). RTL ...

  • GPU Design Verification Engineer

    Intel - Folsom, California
    ... the logic design, register transfer level (RTL) coding, and simulation for Display graphics IP ... designs. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify ...

  • SoC RTL Designer Engineer

    Intel - Folsom, California
    ... efficient low latency designs with scalabilities and flexibilities Power and Area efficient RTL logic ... multiple power domains, UPF, Power state tables. High performance digital logic designs and ...

  • FPGA Design Engineer

    Intel - San Jose, California
    ... time in the future. Altera® has been delivering industry-leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984. To take advantage of the ...

  • CIT RTL verification

    Intel - Folsom, California
    ... Computer Science/Engineering and/or Electrical Engineering. 1+ years’ experience with digital logic ...

  • Physical Design Engineer – Graduate Intern

    Intel - Sacramento, California
    ... collaborate with architects, logic designers, and analog engineers in evaluating implementation details of ... floor planning, Power supply and power grid planning and analysis, Logic synthesis of design blocks ...

  • Physical Design Engineer Intern

    Intel - Sacramento, California
    ... will collaborate with architects, logic designers, and analog engineers in evaluating implementation ... power grid planning and analysis, Logic synthesis of design blocks. Formal Equivalence Verification ...

  • Intel Mask Operation Module Development Engineer

    Intel - Santa Clara, California
    ... Job Description This position is in the Logic Technology Development team working in one ... Work. Find more information about our Amazing Benefits here. What we do: The Logic ...

  • Standard Cell Design Engineer

    Intel - Santa Clara, California
    ... CMOS combinatorial logic and sequential element design and layout. VLSI Design Automation ... , including CMOS combinatorial logic and sequential element design and layout. Understanding of device ...

  • Lab Engineering Technician

    Intel - Folsom, California
    ... . Synthesize complex and non-complex information. Use logic and deductive reasoning to solve problems ...

  • FPGA Development Tools Engineering Director

    Intel - San Jose, California
    ... support. Leverages knowledge of FPGA hardware, logic design, board design, semiconductors and chip layout ...

  • Lab Engineering Technician

    Intel - Folsom, California
    ... . Synthesize complex and non-complex information. Use logic and deductive reasoning to solve problems ...

  • Design Engineer - Foundry Services

    Intel - Folsom, California
    ... : Logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries ... Architecture and Microarchitecture specifications for the Logic components. Provide IP integration ...

  • Discrete Graphics Hardware Engineer

    Intel - Santa Clara, California
    ... efficient RTL logic design, and DV support - Running tools to ensure lint-free and CDC/RDC clean design ... in modern design techniques and energy-efficient/low power logic design and power analysis ...

  • GPU Validation Engineer

    Intel - Folsom, California
    ... analytical skills. Experience and hands on skills with LTB, ITP, Logic Analyzers, Oscilloscopes, Scan ...
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