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Apple
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Cupertino, California
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Support all front end integration activities like Lint, CDC, Synthesis, and ECO - Implement design
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Apple
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Cupertino, California
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aggressive power targets • Support the DV team in verification closure for achieving first pass silicon
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Apple
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Cupertino, California
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SystemVerilog - Support font-end integration activities e.g. CDC, Synthesis, low power flows - Work with SOC
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Apple
-
Cupertino, California
...
SystemVerilog - Support font-end integration activities e.g. CDC, Synthesis, low power flows - Work with SOC
...