Job Description

• Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches.

• Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals.

• Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design.

• Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues.

• Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers.

• Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities.

Qualifications

Candidate should possess a BSEE or equivalent with 3+ years/MSEE or equivalent with 5+ years design experience in the structural/physical design domain.

Additional qualifications include:

• Delivery of multiple partitions in SoCs, ASICs, or Sub Chips

• Expertise in FEV. VCLP and Other RTL checks

• Proficient in all aspects of physical design from RTL - GDSII (Synthesis, Floorplan, Auto Place and Route, Clock Tree Synthesis).

• Expert level knowledge on Synopsys based implementation tools - ICC2, Fusion Compiler

• Experienced in CTS methodologies - CTS, MPCTS, CTMESH

• Expertise in High frequency timing closure at sub chip or at SoC

• Experienced in Full chip Layout Verification - DRC and LVS

• Experience on 7nm and lower a plus

• Possesses - Strong Technical Aptitude, Self-Driven, Analytical, Ability to work in diverse teams and Ability to multi-task.

• Motivated and Passionate to learn improvements in tool flows and methodologies

• Good Communication Skills - Partner with multiple stake holders to deliver the key responsibilities

• Hands-on experience with scripting languages such as Python, Perl, TCL

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

IN, Bangalore

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.