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SpaceX
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Sunnyvale, California
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Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis ... .
Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock
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SpaceX
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Hawthorne, California
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logic designs and signals processing algorithms in RTL
Integrate designs onto FPGA/SoC ... )
As an FPGA Engineer on the Falcon team, you will design and implement signal processing chains needed
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SpaceX
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Hawthorne, California
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Implement logic designs and signals processing algorithms in RTL
Integrate designs onto FPGA/SoC ... )
As a Sr. FPGA Engineer on the Falcon team, you will design and implement signal processing chains
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SpaceX
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Irvine, California
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Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis ... unified power format and power intent verification
Some logic design in Verilog/SystemVerilog
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SpaceX
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Redmond, Washington
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Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Redmond, WA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
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SpaceX
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Irvine, California
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Irvine, CA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
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SpaceX
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Sunnyvale, California
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Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Sunnyvale, CA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
...
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SpaceX
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Sunnyvale, California
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Sunnyvale, CA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
...
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SpaceX
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Redmond, Washington
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Redmond, WA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
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SpaceX
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Irvine, California
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Principal SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX
Irvine, CA ... EXPERIENCE:
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
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SpaceX
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Irvine, California
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Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) at SpaceX
Irvine, CA ... development and integration
Responsible for RTL design, synthesis, timing constraints, power
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SpaceX
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Sunnyvale, California
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Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) at SpaceX
Sunnyvale, CA ... development and integration
Responsible for RTL design, synthesis, timing constraints, power
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SpaceX
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Redmond, Washington
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Sr. ASIC Design Engineer, DDR IP (Silicon Engineering) at SpaceX
Redmond, WA ... development and integration
Responsible for RTL design, synthesis, timing constraints, power
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