At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Work with R&D to identify and scope opportunities for the Cadence functional logic verification platform

• Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues

• Summarize the tasks and projects, and report to manager and share with team effectively

• Train, ramp-up and accompany customer project.

• Conduct basic and advanced trainings, presentations and demos as necessary.

• Ramp-up other members of the team on the advanced verification technologies and tools.

• Providing technical expertise to address clients’ queries, which need expert involvement

Requirements

• The candidate should possess minimum BS level of CS or EE with 10+ years of industry experience.

• Minimum 10 years hands-on, high expertise on hardware design & verification techniques.

• Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.

• Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.

• Understanding standard BUS protocol like AMBA or interface protocol.

• Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.

• Experience on UVM methodology or similar one should be preferred.

• Hands on Design experience using SystemVerilog, Verilog and VHDL.

• Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.

• Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.

• Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.

• Good communication skills in English and a strong desire for working in a global environment with customers and BU people.

• The candidate should possess minimum BS level of CS or EE with 10+ years of industry experience.

• Minimum 10 years hands-on, high expertise on hardware design & verification techniques.

• Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.

• Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.

• Understanding standard BUS protocol like AMBA or interface protocol.

• Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.

• Experience on UVM methodology or similar one should be preferred.

• Hands on Design experience using SystemVerilog, Verilog and VHDL.

• Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.

• Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.

• Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.

• Good communication skills in English and a strong desire for working in a global environment with customers and BU people.

  We’re doing work that matters. Help us solve what others can’t.

Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.