Job Information
Siemens Digital Industries Software Application Engineer Manager - Design Verification Technology in Seongnam, South Korea
Job Family: Sales
Req ID: 409894
At Siemens, we are always challenging ourselves to build a better future.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.
Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.
Key Responsibilities
Manage and guide AE team supporting DVT products in Korea
Communicate with sales team and qualify the business opportunity with DVT factory side
Provide technical support to customers via telephone and other electronic means, and at customer locations
Assist customers and team in deploying Siemens EDA's Questa to solve design challenges
Track and update customer issues using defined Siemens EDA's processes and tracking tools
Develop team’s technical content for Siemens EDA's knowledge base
Communicate customers' technical requirements as well as customer issues to the product and sales team
Qualifications
More than 10 years experiences related with register-transfer-level (RTL) digital logic design, functional verification methodology, static and formal verification, and FPGA & emulation a plus
Bachelor’s degree in EE and related field is required
Strong written and oral communications in the English language is a plus
Build strong rapport and credibility with customer organizations while maintaining a company internal network of contacts
With strong communications and interpersonal skills
This experience should include some of the followings:
Job Experience Requirement
Familiar with System Verilog, UVM is must
Verification of Full SoC and IP level : Verilog RTL simulation is must, Validation of IP on FPGA platform is a plus
SOC work & verification with ARM Cores, protocols like AXI, ACE, APB...a plus
Familiar with mobile AP, memory spec. like DDR, LPDDR is a plus
Familiar with FuSa chip design or requirements is a plus
Tool Experience
Design and Simulation in RTL : Verilog-HDL, NC-Verilog, Xcelium, Questa, VCS
RTL Debugger: DVE, Verdi, Indago & Visualizer
Logic Synthesis : DC Complier is a plus
Power verification : Power Pro, Spyglass, UPF flow verification is a plus
FuSa: VC-Z01X, Xcelium-Safety is a plus
Desirable Qualifications
System Verilog, OVM/UVM, SVA
SystemC, C/C++, Tcl/TK, PERL as a plus
Synthesis, CDC and Static timing analysis as a plus
IS026262 specification certification is a plus
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Siemens Digital Industries Software
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