ESSENTIAL DUTIES AND RESPONSIBILITIES

• Leadership and Team Management:
• Lead and manage a team of engineers in the design and development of ASIC (Application-Specific Integrated Circuit) designs.
• Mentor and coach team members, fostering a collaborative and innovative environment.
• Manage project schedules, deliverables, and resource allocation to ensure timely and successful completion of design projects.
• ASIC Design Process Oversight:
• Manage architecture specification, RTL design , FPGA based emulation and board level hardware development
• Oversee physical design activities contracted to a third-party ASIC Vendor , including synthesis, static timing, layout, DFT, DRC/LVS checks, power integrity analysis , test vector generation and ASIC qualification
• Collaborate with cross-functional teams (e.g., Architecture, Verification, System test, Hardware, and physical design) to ensure design consistency and integration
• Technical Direction and Innovation:
• Provide technical direction on ASIC architecture, design methodologies, and design best practices.
• Identify and implement design optimizations for performance, power, and area (PPA).
• Stay up to date with industry trends and emerging technologies, guiding the team toward innovative solutions.
• Stakeholder Communication and Collaboration:
• Coordinate with external ASIC vendors, foundries, and EDA tool providers to ensure design flows and tools are up to standard.
• Communicate project status, risks, and deliverables to senior management and stakeholders.
• Support post-silicon activities, including bring-up, validation, and debug.
• Risk Management and Problem-Solving:
• Identify potential design risks and work proactively to mitigate them.
• Resolve design and integration issues that arise during the development cycle.

Qualifications

REQUIRED

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital design principles, ASIC design methodologies, Physical design and verification.
• Minimum of 5 years of experience in ASIC design, including RTL design, synthesis, timing closure, and verification.
• Proven track record of managing or leading ASIC design projects from conception to tape-out.
• Hands-on experience with ASIC design tools such as Cadence, Synopsys, or Mentor Graphics.

SKILLS

• Proficiency in HDL languages (e.g., Verilog, VHDL) and scripting languages (e.g., Python, Perl, TCL).
• Understanding of physical design concepts, including synthesis, floor planning, and timing analysis.
• Knowledge of DFT (Design for Test) and low-power design techniques.
• Experience with hardware development, post-silicon validation, debug, and bring-up processes.
• Strong leadership and people management skills.
• Excellent communication and collaboration abilities to work with cross-functional teams and external stakeholders.
• Problem-solving mindset with a keen eye for detail and quality.

PREFERRED

• Experience with mixed-signal design or working in advanced process nodes (e.g., 7nm, 5nm).
• Familiarity with system-level architecture and integration, including interface protocols such as PCIe or Ethernet.
• Knowledge of storage protocols like Fiber Channel, SCSI, SAS, SATA, NVMe or NVMe over fabrics will be a plus