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Intel
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Hillsboro, Oregon
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and design for the next generation of laptop and desktop computers. We are looking for an SoC (System on Chip) Front-End Engineer, ready to research, design, develop, and test lead Intel designs as we
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Intel
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Hillsboro, Oregon
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two or more of the following areas:
Computer architecture
RTL design
Digital logic and optimizations ... and design for the next generation of laptop and desktop computers.
We are looking for an SoC (System
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Intel
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Hillsboro, Oregon
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related fields.
Experience in the following:
Logic/RTL design.
Digital architecture ... following but not limited to:
Oversees definition, design, verification, and documentation for SoC
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Intel
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Hillsboro, Oregon
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and design for the next generation of laptop and desktop computers.
We are looking for an SoC (System on Chip) Front-End for Analog Design Engineer ready to research, design, develop, and test lead
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Intel
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Hillsboro, Oregon
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Job Description
Come join the Extreme Scale Computing team as a Logic Design Engineer ... handshake logic between IP and SOC and integrate them.
Working with architects and design engineers to
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Intel
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Hillsboro, Oregon
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, performing Logic design for integration of cell libraries, functional units and subsystems into SoC full chip ... failing RTL tests to ensure correctness of features.
The CPU RTL Design Engineer should possess the
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Intel
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Hillsboro, Oregon
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Engineer in IFS, you will:
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or
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Intel
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Hillsboro, Oregon
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product setting - floor planning, RTL design, circuit simulation, logic synthesis, place and route, clock ... .
About the Role:
The TD/DE EDA Design Flow Development Director reports to VP of Library and SoC
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Intel
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Hillsboro, Oregon
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circuit/subsystem/full chip design via logic, design/RTL/simulation/placement-and-routing/timing/power ... digital IP or ASIC/SoC design / validation / design-for-test etc with RTL and relevant tools
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Intel
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Hillsboro, Oregon
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will:
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component
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Intel
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Hillsboro, Oregon
...
:
Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
Performs
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Intel
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Hillsboro, Oregon
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tools for high speed CPU core design.
Perform all aspects of design flow from logic synthesis ... :
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and
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Intel
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Hillsboro, Oregon
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architects to define, implement the handshake logic between IP and SOC and integrate them.
Working with ... Microarchitecture Specification (MAS) and develop RTL for logical blocks.
Collaborate with design verification
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Intel
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Hillsboro, Oregon
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of all aspects of digital SoC in a product setting - floorplanning, RTL design, logic synthesis ... 's charter.
About the Role:
Design flow development engineer will work in a team responsible
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Intel
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Hillsboro, Oregon
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wonderful for everyone.
DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... Design Engineer should possess the following attributes:
Excellent communication: Expected to
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Intel
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Hillsboro, Oregon
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wonderful for everyone.
DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... Design Engineer should possess the following attributes:
Excellent communication: Expected to
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Intel
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Hillsboro, Oregon
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wonderful for everyone.
DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and ... Design Engineer should possess the following attributes:
Excellent communication: Expected to
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Intel
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Hillsboro, Oregon
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Job Description
Register file (RF) memory design automation engineer. You will be part ... .
Experience in the following:
IC design methodology using standard cells - RTL, schematics, layout
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Intel
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Hillsboro, Oregon
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, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area ... -performance applications.
Responsibilities:
Develop the logic design, register transfer level
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