Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, a relevant technical field, or equivalent practical experience.

• 8 years of experience with DFT/DFD flows and methodologies.

• Experience with DFT/DFM technique and well-versed in ATPG, MBIST, JTAG, Scan Compression, SSN and at-speed test.

• Experience with silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues.

• Experience with post-silicon electrical/physical fault isolation.

Preferred qualifications:

• Experience with scripting languages like Python, Perl, etc.

• Experience with silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and diagnostics.

• Knowledge of defect types, fault models, and low power design methodologies.

• Ability to be motivated and collaborate with global teams.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Be responsible for delivering Design For Excellence (DFX) solutions and ensuring first time right silicon for multiple complex and high performance SoC designs in advanced technology nodes.

• Help develop and deploy DFT methodologies for our next generation products.

• Work closely with internal design teams to define requirements (DFT) to support Silicon debug.

• Define the required Electrical Failure Analysis (EFA) workflows for various cases (e.g., Yield, Qualification, Customer Returns).

• Drive root causing yield issues, qualification failures, customer issues or any event that requires investigation and problem solving techniques to debug and root cause failing Silicon.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.