Graphics Physical Design PPA Engineer

Austin,Texas,United States

Hardware

Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day!

Key Qualifications

• We are looking for candidates with 3+ years of design implementation experience, including:

• Knowledge of logic design principles, physical design aspects as well as power, timing and DFT concepts.

• Experience with industry standard synthesis, physical design and STA tools.

• Scripting proficiency with TCL, Perl.

• Knowledge of circuit layout and experience with spice tools is highly desirable.

• Analytical & data mining skills to draw conclusions from large amounts of data.

• Fast learner and highly motivated to solve technical challenges using innovation.

• Strong verbal/communication skills; ability to work effectively with various functional teams and drive task to completion.

Description

In this role, you will be involved with enablement and bring-up of the latest technology nodes and projecting Performance, Power and Area for the next generation graphics chips. Your responsibilities include: • Work closely with the Front-End and Physical Design teams to drive methodology changes to improve performance, power and area for the next generation GPU designs and recommend design/methodology changes to absorb the updates. • Work with the Apple custom design teams to analyze the standard cell and memory hard-IP offerings and recommend usage to the graphics FE/PD teams. • Drive design of custom cells tailored specifically for GPU design requirements. • Work with power teams to analyze GPU power and make recommendations for power reduction across architecture and gate-level design.

Education & Experience

We are looking for candidates with a minimum of BS + 3 years of experience.

Additional Requirements

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